1. Field
Example embodiments relate to a structure for blocking an electromagnetic interference, a wafer level package and a printed circuit board having the same. More particularly, example embodiments relate to a structure for protecting circuits of electronic devices from an electromagnetic interference, a wafer level package and a printed circuit board having the same.
2. Description of the Related Art
Generally, various semiconductor fabrication processes may be performed on a semiconductor substrate to form a plurality of semiconductor chips. In order to mount the semiconductor chips on a printed circuit board (PCB), a packaging process may be performed on the semiconductor chips to form semiconductor packages.
According to a conventional packaging method, a wafer may be cut along a scribe lane to divide the wafer into semiconductor chips. The semiconductor chips may be attached to a package substrate. Bonding pads of the semiconductor chips may be electrically connected with the package substrate using conductive wires. A molding member may be formed on the package substrate to surround the semiconductor chips with the molding member. External terminals, e.g., solder balls, may be mounted on the package substrate.
However, because the conventional packaging method may be separately performed on each of the semiconductor chips, the conventional packaging method may have low efficiency.
In order to solve the above-mentioned problem, a wafer level packaging method may be proposed. According to the wafer level packaging method, after a packaging process may be performed on the wafer, the wafer may then be cut to form wafer level packages.
The wafer level package may include a semiconductor chip having bonding pads, a first insulating layer, a conductive layer pattern, a second insulating layer pattern and conductive bumps. The first insulating layer pattern may be formed on a first surface of the semiconductor chip. Further, the first insulating layer pattern may have openings configured to expose the bonding pads. The conductive layer pattern may be formed on the first insulating layer pattern. The conductive layer pattern may have a first end electrically connected to the bonding pads. The second insulating layer pattern may be formed on the first insulating layer pattern. The second insulating layer pattern may have an opening configured to expose a second end of the conductive layer pattern opposite to the first end. The conductive bumps may electrically make contact with the second end of the conductive layer pattern.
The wafer level package may have a weak structure with respect to electromagnetic interference (EMI), because the wafer level package may not be surrounded with a molding member. In order to decrease the EMI, an electromagnetic wave filter layer including a ferrite material may be formed on a second surface of the semiconductor chip opposite to the first surface.
However, the electromagnetic wave filter layer may not surround entire surfaces of the wafer level package due to an electrical short. Thus, the wafer level package may still have a weak structure with respect to the EMI.